Synopsys Expands AI and Multi-Die Design Collaboration with Samsung Foundry

Synopsys announced new collaborations with Samsung Foundry at the Samsung Advanced Foundry Ecosystem (SAFE) Forum 2026, announced in a press release. The partnership expands production ready AI powered electronic design automation tools, certified interface IP, and silicon based test capabilities for advanced 2nm and 4nm processes.

The new Synopsys digital and analog flows are production ready for Samsung Foundry’s third generation 2nm class process. These flows, developed through joint design technology co optimization, deliver measurable improvements in power, performance, and area compared to the previous generation. Synopsys Fusion Compiler demonstrated validated performance gains on this process.

Synopsys also introduced signoff solutions with certified multiphysics capabilities, including PrimeShield Process Sensitivity Analysis and PVT Explorer, which optimize performance and leakage tradeoffs based on silicon feedback. The Totem-SC tool was certified for electromigration and IR drop analysis on 2nm and 4nm processes to enhance power integrity and reliability.

AI powered test solutions were highlighted, with Synopsys TestMAX achieving up to 20 percent test efficiency improvements through AI assisted automatic test pattern generation, validated in collaboration with Samsung Foundry. These methods aim to reduce test cost and cycle time while maintaining fault coverage for system on chip and multi-die designs.

The companies also presented a unified exploration to signoff platform within Synopsys 3DIC Compiler, validated on Samsung’s Hybrid Copper Bonding technology. This platform integrates planning, implementation, and multiphysics analysis for scalable 3D multi-die designs. Additionally, Synopsys expanded its certified IP portfolio across Samsung’s advanced and automotive nodes to reduce integration risk and accelerate time to market.