Tesla outlines SI6 and Dojo 3 chips in revised AI accelerator roadmap
Tesla outlines a revised accelerator roadmap that includes its SI6 inference chip and Dojo 3 training chip, reports Tom's Hardware. The company is also replacing artificial intelligence branding with super intelligence and renaming its accelerators under SI labels.
Dojo 3, also called D3, will combine multiple chiplets, advanced packaging and stacked high bandwidth memory. The design differs from Dojo D1, which used wafer scale packaging and relied on on chip SRAM. Tesla has not disclosed D3's compute performance, memory capacity, manufacturing process or launch schedule.
The roadmap places SI6 in 2029 to 2030 and lists 80 times the compute performance and nine times the memory of SI4. SI4 is Tesla's current vehicle inference processor and the baseline for its Full Self Driving system, but the company does not publish its absolute compute performance.
We hope you enjoyed this article
Consider subscribing to one of our newsletters like Silicon Brief or Daily AI Brief.
Also, consider following us on social media:
More from Data Centers
Nov 6 ING auctions $500 million of data center loans, including a Stargate piece Nov 6 More Than 100 Protesters Enter Microsoft Data Center Site in Amsterdam Nov 6 NTT DATA signs 900MW Bloom Energy fuel cell deal for its data centers Nov 6 Interior Secretary Burgum holds up to $64.4 million in AI investments, ProPublica finds Nov 6 Innodisk Q3 revenue rises 579.9% as AI sales exceed 40%Silicon Brief
Weekly coverage of AI hardware developments including chips, GPUs, cloud platforms, and data center technology.
Whitepaper
Tensordyne Napier: What If One Rack Could Do the Work of Nine?
Tensordyne
This Tensordyne whitepaper presents Napier, an inference-focused AI processor and rack-scale system based on the company’s TDN Math logarithmic number system. It examines infrastructure requirements for large mixture-of-experts and agentic models, compares major inference architecture approaches, and details the TDN AIP processor, TDN72 pod, TDN Link fabric, and Napier Ultra configuration. The paper reports simulation-based performance, cost, and accuracy-validation results, including Tensordyne’s projected comparison of one Napier rack with a nine-rack Nvidia Rubin plus Groq deployment; the chip is reported as taped out and in fabrication.
Read moreYou may also like
AI Chip Market Forecast to Reach $677.59 Billion by 2035
FuriosaAI Raises $620 Million to Scale Inference Chip Production
BrainChip launches Sequora core for generative AI on battery powered devices
Tenspresso Seeks $50 Million at $500 Million Valuation
DeepSeek and Huawei Collaborate on Ascend AI Chips
Daily AI Brief: the AI news that matters, in your inbox.