NEO Semiconductor Unveils X-HBM for AI Chips

NEO Semiconductor has introduced the world's first Extreme High Bandwidth Memory (X-HBM) architecture for AI chips, announced in a press release. This new architecture offers a 32K-bit wide data bus and potentially 512 Gbit per die density, providing 16 times more bandwidth or 10 times higher density compared to traditional HBM.

Built on NEO's proprietary 3D X-DRAM architecture, X-HBM is designed to meet the increasing demands of generative AI and high-performance computing. It significantly surpasses the capabilities of current memory technologies, such as HBM5 and the projected HBM8, by eliminating long-standing limitations in bandwidth and density.

NEO Semiconductor's CEO, Andy Hsu, emphasized that X-HBM is a fundamental breakthrough, offering AI chipmakers a path to deliver next-generation performance well ahead of the existing roadmap. The company will showcase this technology at the Future of Memory and Storage event in Santa Clara, California.