Arasan Chip Systems Introduces 16-Bit Sureboot Total xSPI + PSRAM IP Solution

Arasan Chip Systems announced in a press release the launch of its Sureboot Total 16-bit xSPI + PSRAM IP solution. The new design integrates a memory controller IP, a PHY IP, and a software stack to provide a complete interface for high performance and low power memory systems.

The Sureboot Total xSPI + PSRAM IP is designed to support AP Memory’s Xccela PSRAM and the latest LVpSRAM, enabling faster data transfer and improved efficiency for system on chip designs. It uses two 8-bit data lanes to deliver 32-bit transfers per clock cycle at 266 MHz and supports both 1.2 V and 1.8 V devices.

The IP complies with the JEDEC JESD251C specification and remains backward compatible with Octal, Quad, and Dual SPI standards. It starts directly in SPI mode for immediate memory access and includes AXI memory mapping with integrated DMA support, simplifying integration for chip developers.