DeepX tapes out 2nm DX-M2 edge AI chip built for 100B-parameter models at 5W

Nov 13, 2026
The South Korean startup's second-generation chip on Samsung's 2nm process triples memory bandwidth; mass production is targeted for autumn 2027.

South Korean edge AI chip startup DeepX has completed tape-out of its second-generation DX-M2 processor on Samsung Foundry's second-generation 2nm (SF2P) process, OODA Loop reports. The chip delivers 80 TOPS and raises external memory bandwidth from 50 GB/s to 150 GB/s, aimed at running language and mixture-of-experts models of 20 billion to 100 billion parameters within a 5-watt budget.

DeepX is testing it with Samsung's LPDDR5X processing-in-memory samples, and simulations project 6.7 times more tokens per second on Llama 3.1 8B at about 2.7 times the total power. First silicon samples are due in March 2027, customer sampling in the second quarter and mass production in autumn 2027, targeting robots and drones.

We hope you enjoyed this article

Consider subscribing to one of our newsletters like Silicon Brief or Daily AI Brief.

Also, consider following us on social media:

AI Chips & Datacenters AI Brief AI Brief (X)
Free newsletter

Silicon Brief

Weekly coverage of AI hardware developments including chips, GPUs, cloud platforms, and data center technology.

Guide
Private AI chip companies, by latest reported valuation

Private AI chip companies, by latest reported valuation

Private companies building AI compute silicon (the chips that run AI workloads), shown with each company's most recent reported or disclosed valuation. The figures are measured on different dates and bases, so this is a snapshot, not a live ranking or a like-for-like comparison.

Whitepaper

Tensordyne Napier: What If One Rack Could Do the Work of Nine?

Tensordyne

This Tensordyne whitepaper presents Napier, an inference-focused AI processor and rack-scale system based on the company’s TDN Math logarithmic number system. It examines infrastructure requirements for large mixture-of-experts and agentic models, compares major inference architecture approaches, and details the TDN AIP processor, TDN72 pod, TDN Link fabric, and Napier Ultra configuration. The paper reports simulation-based performance, cost, and accuracy-validation results, including Tensordyne’s projected comparison of one Napier rack with a nine-rack Nvidia Rubin plus Groq deployment; the chip is reported as taped out and in fabrication.

Read more

You may also like

Free, six days a week

Daily AI Brief: the AI news that matters, in your inbox.