Huawei Presents Tau Scaling Law as Successor to Moore’s Law

Huawei has introduced the Tau (τ) Scaling Law as a new principle to guide semiconductor development, announced in a press release. The concept, presented by He Tingbo, President of Huawei’s Semiconductor Business Department, at the 2026 IEEE International Symposium on Circuits and Systems in Shanghai, replaces traditional geometric transistor scaling with time scaling as the main measure of progress.

The Tau Scaling Law focuses on reducing signal propagation delay and system execution time to improve performance, energy efficiency, and transistor density. Huawei is developing supporting technologies such as LogicFolding and a multi-level optimization framework that spans devices, circuits, chips, and systems to minimize physical-layer delay.

At the circuit level, LogicFolding restructures layouts to shorten critical signal paths, improving transistor density and circuit performance. At the chip level, the company coordinates software, architecture, and silicon design to optimize data flow and parallel processing. At the system level, Huawei’s UnifiedBus interconnect protocol enables unified memory addressing to reduce communication latency in large computing systems.

Huawei stated that it has already applied the Tau Scaling Law to smartphones and AI computing, producing 381 chips under the new framework over the past six years. The upcoming Kirin processors, planned for release in fall 2026, will be the first to feature the LogicFolding architecture. Huawei projects that by 2031, high-end chips developed under this framework could achieve transistor densities comparable to 1.4 nm process technologies.