Aion Silicon Secures $12M for RISC-V Accelerator Program

May 29, 2025
Aion Silicon has announced a $12 million engagement to develop RISC-V accelerators for high-performance computing and AI, leveraging its extensive SoC expertise.
Aion Silicon Secures $12M for RISC-V Accelerator Program

Aion Silicon has announced in a press release that it has secured a $12 million engagement to provide comprehensive design services for a confidential customer. The project focuses on developing next-generation RISC-V-based accelerators for high-performance computing (HPC) and artificial intelligence (AI).

The multi-year program will utilize Aion Silicon's extensive experience in System-on-Chip (SoC) architecture to introduce energy-efficient processors aimed at handling compute-intensive workloads in data centers and scientific research globally. The company will deliver a full range of design services, including RTL architecture, verification, and physical implementation on a cutting-edge RISC-V platform.

Aion Silicon's CEO, Oliver Jones, emphasized the importance of developing accelerators that offer extreme performance per watt, highlighting the company's ability to transform innovative RISC-V architectures into manufacturable silicon. The engineering work is already underway, with plans for additional hires through 2025 as the project progresses towards tape-out and initial silicon production.

We hope you enjoyed this article

Consider subscribing to one of our newsletters like AI Funding Brief, Silicon Brief or Daily AI Brief.

Free newsletter

Silicon Brief

Weekly coverage of AI hardware developments including chips, GPUs, cloud platforms, and data center technology.

Whitepaper

Tensordyne Napier: What If One Rack Could Do the Work of Nine?

Tensordyne

This Tensordyne whitepaper presents Napier, an inference-focused AI processor and rack-scale system based on the company’s TDN Math logarithmic number system. It examines infrastructure requirements for large mixture-of-experts and agentic models, compares major inference architecture approaches, and details the TDN AIP processor, TDN72 pod, TDN Link fabric, and Napier Ultra configuration. The paper reports simulation-based performance, cost, and accuracy-validation results, including Tensordyne’s projected comparison of one Napier rack with a nine-rack Nvidia Rubin plus Groq deployment; the chip is reported as taped out and in fabrication.

Read more
Free, six days a week

Daily AI Brief: the AI news that matters, in your inbox.