Arasan Chip Systems Releases UFS 5.0 Host Controller IP
Arasan Chip Systems has announced the immediate availability of its UFS 5.0 host controller IP, according to a press release. The IP is already in use by testing companies for compliance and production validation.
The UFS 5.0 host controller IP supports a maximum data rate of 46.694 Gbps using M-PHY HS-Gear 6 mode. It is designed to deliver high-speed data transfer with low power consumption for mobile devices and AI edge systems. Arasan has been a member of the UFS Association since 2010 and was the first in the industry to provide a complete UFS IP solution.
The new IP extends Arasan’s portfolio of semiconductor memory solutions, which includes xSPI and PSRAM IP for NOR Flash, eMMC controllers for low-bandwidth NAND applications, and integrated NAND Flash controller IP with PHY. The UFS 5.0 host controller IP is available for both FPGA and ASIC implementations along with its associated M-PHY Digital Front End and UFS 5.0 software stack.
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