Synopsys and TSMC Expand AI Chip Design Partnership

Synopsys and Taiwan Semiconductor Manufacturing Company Limited (TSMC) announced in a press release an expanded collaboration covering agentic AI workflows, electronic design automation, advanced packaging, and semiconductor IP. The companies will provide certified Synopsys design flows for TSMC A14 digital and analog designs, spanning implementation through signoff.

The collaboration includes agentic AI workflows for analog, digital, and multi die designs using Synopsys Custom Compiler, Fusion Compiler, and 3DIC Compiler. It also supports the co design and simulation of integrated voltage regulators for TSMC CoWoS technology, along with photonic and electronic co design for TSMC COUPE technology.

Synopsys is also expanding its interface, foundation, and silicon lifecycle management IP for TSMC processes including N2P and N3P. The work covers PCIe 7.0, HBM4, LPDDR6, Ethernet, UCIe, and process monitoring IP, including a demonstration of UCIe A 32G and 40G silicon on a TSMC N3P test chip with a CoWoS S interposer.