PATEO and Aumovio Sign Cooperation Agreement on High Computing SDV and AGI Technologies

Apr 28, 2026
PATEO CONNECT Technology and Aumovio Holding China have signed a memorandum of understanding to jointly develop high computing platforms and artificial general intelligence technologies for software defined vehicles, focusing on global market expansion.

PATEO CONNECT Technology and Aumovio Holding China have signed a memorandum of understanding to collaborate on high computing and artificial general intelligence technologies for software defined vehicles, announced in a press release at the Beijing International Automotive Exhibition on April 25.

The agreement outlines joint development of cross domain integrated product solutions based on high computing system on chip platforms. Both companies will form a joint team to focus on demonstration projects for AGI automotive applications. The collaboration aims to combine expertise in technology, products, customers, supply chain, and production to expand global SDV domain control and AGI application businesses.

PATEO and Aumovio will work together on high computing SDV technologies through joint investment and technology collaboration. The partnership supports PATEO's strategy of combining AI development with global market expansion and strengthens its position in intelligent mobility and SDV technology fields.

We hope you enjoyed this article

Consider subscribing to one of our newsletters like Enterprise AI Brief or Daily AI Brief.

Also, consider following us on social media:

Free newsletter

Enterprise AI Brief

Weekly report on AI business applications, enterprise software releases, automation tools, and industry implementations.

Whitepaper

Tensordyne Napier: What If One Rack Could Do the Work of Nine?

Tensordyne

This Tensordyne whitepaper presents Napier, an inference-focused AI processor and rack-scale system based on the company’s TDN Math logarithmic number system. It examines infrastructure requirements for large mixture-of-experts and agentic models, compares major inference architecture approaches, and details the TDN AIP processor, TDN72 pod, TDN Link fabric, and Napier Ultra configuration. The paper reports simulation-based performance, cost, and accuracy-validation results, including Tensordyne’s projected comparison of one Napier rack with a nine-rack Nvidia Rubin plus Groq deployment; the chip is reported as taped out and in fabrication.

Read more
Free, six days a week

Daily AI Brief: the AI news that matters, in your inbox.