InPsytech Showcases 3nm UCIe 3.0 Chiplet Technology at OCP Global Summit 2025

Oct 13, 2025
InPsytech presented its 3nm UCIe 3.0 high-speed interface technology at the OCP Global Summit 2025 in San Jose, demonstrating support for 3D packaging and collaboration with Alcor Micro on an Arm-based CPU platform.

InPsytech, a subsidiary of Egis Technology, showcased its 3nm UCIe 3.0 high-speed interface technology at the OCP Global Summit 2025 in San Jose, California, announced in a press release. The demonstration featured full UCIe 3.0 standard compliance, 3D packaging integration, and data transfer rates up to 64 GT/s, emphasizing low power consumption and high efficiency for chiplet interconnects.

The company’s UCIe portfolio supports process nodes from 22nm down to 2nm and is optimized for 3nm production. The showcased technology highlights InPsytech’s focus on enabling chip-to-chip interconnects for heterogeneous integration in advanced semiconductor designs.

In collaboration with Alcor Micro, InPsytech’s UCIe technology has been integrated into Alcor’s Arm-based CPU platform, Mobius100 (CSS V3). The platform, built on Arm Neoverse CSS architecture, supports die-to-die interconnects and integration with GPUs, NPUs, and AI accelerators. Both companies are members of the Arm Total Design program, contributing to the development of the Arm chiplet ecosystem.

We hope you enjoyed this article

Consider subscribing to one of our newsletters like Silicon Brief or Daily AI Brief.

Also, consider following us on social media:

AI Chips & Datacenters AI Brief AI Brief (X)
Free newsletter

Silicon Brief

Weekly coverage of AI hardware developments including chips, GPUs, cloud platforms, and data center technology.

AI Token Webinar

Whitepaper

Tensordyne Napier: What If One Rack Could Do the Work of Nine?

Tensordyne

This Tensordyne whitepaper presents Napier, an inference-focused AI processor and rack-scale system based on the company’s TDN Math logarithmic number system. It examines infrastructure requirements for large mixture-of-experts and agentic models, compares major inference architecture approaches, and details the TDN AIP processor, TDN72 pod, TDN Link fabric, and Napier Ultra configuration. The paper reports simulation-based performance, cost, and accuracy-validation results, including Tensordyne’s projected comparison of one Napier rack with a nine-rack Nvidia Rubin plus Groq deployment; the chip is reported as taped out and in fabrication.

Read more

You may also like

Free, six days a week

Daily AI Brief: the AI news that matters, in your inbox.