MIPS and Cyient Semiconductor Collaborate on RISC-V Power Solutions

Jun 14, 2025
MIPS and Cyient Semiconductor have announced a strategic collaboration to develop RISC-V-based intelligent power solutions for automotive, industrial, and data center markets.

MIPS and Cyient Semiconductor have announced a strategic collaboration to develop custom RISC-V-based intelligent power solutions, announced in a press release. The partnership aims to create domain-optimized ASIC and ASSP solutions leveraging MIPS' Atlas portfolio of processor IP, focusing on real-time, safety-critical applications, power delivery, and compute efficiency.

The collaboration will target applications in automotive, industrial robotics, and data centers, with a particular emphasis on motor control and data center power delivery. By combining MIPS' advanced processor IP with Cyient's expertise in analog mixed-signal design, the partnership seeks to offer differentiated solutions that meet the unique needs of OEMs and system integrators.

This initiative is driven by the growing demand for software-defined vehicles, data center infrastructure, and industrial automation, which require advanced, easy-to-program solutions. The collaboration promises faster time-to-market and optimized platform costs, avoiding proprietary lock-ins.

We hope you enjoyed this article

Consider subscribing to one of our newsletters like Silicon Brief or Daily AI Brief.

Also, consider following us on social media:

AI Chips & Datacenters AI Brief AI Brief (X)
Free newsletter

Silicon Brief

Weekly coverage of AI hardware developments including chips, GPUs, cloud platforms, and data center technology.

AI Token Webinar

Whitepaper

Tensordyne Napier: What If One Rack Could Do the Work of Nine?

Tensordyne

This Tensordyne whitepaper presents Napier, an inference-focused AI processor and rack-scale system based on the company’s TDN Math logarithmic number system. It examines infrastructure requirements for large mixture-of-experts and agentic models, compares major inference architecture approaches, and details the TDN AIP processor, TDN72 pod, TDN Link fabric, and Napier Ultra configuration. The paper reports simulation-based performance, cost, and accuracy-validation results, including Tensordyne’s projected comparison of one Napier rack with a nine-rack Nvidia Rubin plus Groq deployment; the chip is reported as taped out and in fabrication.

Read more

You may also like

Free, six days a week

Daily AI Brief: the AI news that matters, in your inbox.