Verkor Introduces VerTQ, TurboQuant Accelerator for LLM Inference

May 20, 2026
Verkor has launched VerTQ, a silicon IP accelerator implementing Google's TurboQuant algorithm to reduce large language model memory usage by over four times while maintaining performance. The chip was autonomously designed by Verkor's Conductor 2.0 AI platform and targets edge AI applications.

Verkor has introduced VerTQ, described as the industry's first TurboQuant accelerator silicon IP, announced in a press release. The technology implements the TurboQuant algorithm developed by Google Research, which cuts key-value cache memory usage in large language models by a factor of 4.3 while maintaining or improving performance.

VerTQ compresses KV data and accelerates attention operations, including Flash Attention and online SoftMax, directly on-chip without decompressing data. This approach reduces memory bandwidth requirements and increases inference efficiency, especially for applications where memory is limited.

The chip was built autonomously by Verkor's Conductor 2.0 AI platform using standard electronic design automation tools. The process took about 80 hours from algorithm to a verified FPGA implementation. Mapped to a Xilinx FPGA running at 125 MHz, VerTQ supports between one and thirty-two attention decoders.

VerTQ is designed for edge AI systems such as autonomous vehicles, drones, and robots, where compact design, low power use, and cost efficiency are key. The VerTQ customer package includes specifications, verification IP, testbenches, and FPGA images, and the product is available now.

We hope you enjoyed this article

Consider subscribing to one of our newsletters like Silicon Brief or Daily AI Brief.

Also, consider following us on social media:

Free newsletter

Silicon Brief

Weekly coverage of AI hardware developments including chips, GPUs, cloud platforms, and data center technology.

Whitepaper

Tensordyne Napier: What If One Rack Could Do the Work of Nine?

Tensordyne

This Tensordyne whitepaper presents Napier, an inference-focused AI processor and rack-scale system based on the company’s TDN Math logarithmic number system. It examines infrastructure requirements for large mixture-of-experts and agentic models, compares major inference architecture approaches, and details the TDN AIP processor, TDN72 pod, TDN Link fabric, and Napier Ultra configuration. The paper reports simulation-based performance, cost, and accuracy-validation results, including Tensordyne’s projected comparison of one Napier rack with a nine-rack Nvidia Rubin plus Groq deployment; the chip is reported as taped out and in fabrication.

Read more
Free, six days a week

Daily AI Brief: the AI news that matters, in your inbox.