Achronix Releases JESD204C IP Core for Speedster7t FPGAs

Achronix Semiconductor Corporation announced in a press release that its JESD204C IP core is now available for the Speedster7t FPGA family. The IP is designed to connect analog to digital converters and digital to analog converters to programmable logic.

The core supports data rates of up to 32 Gbps per lane. Achronix says each link can reach an aggregate serial line rate of up to 256 Gbps, while four cores can provide up to 1 Tbps in aggregate performance.

The standards based core supports JESD204B and JESD204C converters from suppliers including Analog Devices and Texas Instruments. It also supports deterministic latency, 64b/66b and 8b/10b encoding, forward error correction, CRC modes, and synchronization for single and multiple channel systems.

The IP package includes a graphical interface in the Achronix ACE design environment, VHDL and Verilog design files, templates, example designs, simulation tools, and testbenches. Achronix is also offering a free time bound evaluation version for Speedster7t FPGAs.